MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 106

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2-8
BG / VF0 / LWP1
BR / VF1 / IWP2
BB / VF2 / IWP3
IWP[0:1] / VFLS[0:1]
Signal Name
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
Controlled by
RCW[DBGC].
See
Controlled by
RCW[DBGC].
See
Controlled by
RCW[DBGC].
See
Controlled by
RCW[DBGC].
See
Function after
Reset
Table
Table
Table 6-8
Table
6-8.
6-8.
6-8.
1
Bus Grant. Indicates external bus status. BG is asserted low
when the external bus arbiter grants ownership of the
external bus to a specific master. This is an active-low signal
and needs an external pull-up resistor to ensure proper
operation and meet signal timing specifications.
Visible Instruction Queue Flush Status 0. This output signal
together with VF1 and VF2 is output by the
MPC561/MPC563 when program instruction flow tracking is
required. VFs report the number of instructions flushed from
the instruction queue in the internal core. See
“Development
Load/Store Watchpoint 1. This output signal reports the
detection of a data watchpoint in the program flow executed
by the RCPU.
Bus Request. Indicates that the external bus has been
requested for external cycle. This is an active-low signal and
needs an external pull-up resistor to ensure proper
operation and meet signal timing specifications.
Visible Instruction Queue Flush Status 1. This output signal
together with VF0 and VF2 is output by the
MPC561/MPC563 when program instruction flow tracking is
required. VFs report the number of instructions flushed from
the instruction queue in the internal core. See
“Development
Instruction Watchpoint 2. This output signal reports the
detection of an instruction watchpoint in the program flow
executed by the RCPU.
Bus Busy. Indicates that the master is using the external
bus. BB is an active-low signal and needs an external
pull-up resistor to ensure proper operation and signal timing
specifications.
Visible Instruction Queue Flush Status 2. This output signal
together with VF0 and VF1 is output by the
MPC561/MPC563 when a program instructions flow
tracking is required. VFs report the number of instructions
flushed from the instruction queue in the internal core.
Instruction Watchpoint 3. This output signal reports the
detection of an instruction watchpoint in the program flow
executed by the internal core.
Instruction Watchpoint [0:1]. These output signals report the
detection of an instruction watchpoint in the program flow
executed by the RCPU.
Visible History Buffer Flush Status [0:1]. These signals are
output by the MPC561/MPC563 to enable program
instruction flow tracking. They report the number of
instructions flushed from the history buffer in the RCPU. See
Chapter 23, “Development
Support,” for more details.
Support,” for more details.
Description
Support,” for details.
Freescale Semiconductor
Chapter 23,
Chapter 23,