MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 261

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The timeout period is calculated as:
Solving this equation using a 4-MHz external clock and a pre-divider of 256 gives:
This gives a range from 64 microseconds, with a PITC of 0x0000, to 4.19 seconds, with a PITC of 0xFFFF.
When a 20-MHz crystal is used with a pre-divider of 256, the range is between 12.8 microseconds to 0.84
seconds.
6.1.10
The software watchdog timer (SWT) prevents system lockout in case the software becomes trapped in
loops with no controlled exit. The SWT is enabled after system reset to cause a system reset if it times out.
The SWT requires a special service sequence to be executed on a periodic basis. If this periodic servicing
action does not occur, the SWT times out and issues a reset or a non-maskable interrupt (NMI), depending
on the value of the SWRI bit in the SYPCR register.
The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is written by software,
the state of the SWE bit cannot be changed.
The SWT service sequence consists of the following two steps:
The service sequence clears the watchdog timer and the timing process begins again. If any value other
than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over.
Freescale Semiconductor
1. Write 0x556C to the software service register (SWSR)
2. Write 0xAA39 to the SWSR
PITRTCLK
Clock
Software Watchdog Timer (SWT)
PITF (PISCR)
(PISCR)
Disable
Clock
PTE
PIT PERIOD
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 6-8. PIT Block Diagram
PIT PERIOD
=
---------------------------------- -
F PITRTCLK
(PISCR)
Modulus
Counter
PITC
16-bit
PITC
+
1
=
PITC
----------------------- -
15625
=
---------------------------------------------- -
〈
ExternalClock
---------------------------------------- -
+
1
PITC
4 or 256
PIE (PISCR)
PS (PISCR)
+
1
〉
System Configuration and Protection
Interrupt
PIT
6-21