MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 780

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.10.3 MPWMSM Description
The purpose of the MPWMSM is to create a variable pulse width output signal at a wide range of
frequencies, independently of other MIOS14 output signals. The MPWMSM includes its own counter, and
thus does not use the MIOS14 counter bus set. However the MPWMSM uses the prescaled clock bus that
originates in the MIOS14 counter prescaler submodule (MCPSM). The MPWMSM pulse width can vary
from 0% to 100%, with up to 16 bits of resolution. The finest output resolution is the MIOS14 CLOCK
period multiplied by two (for a MIOS14 CLOCK with f
resolution is 50 ns). With the full 16 bits of resolution and the MCPSM set to divide by two, the period of
the output signal can range from 3.276 ms to 6.71 s (assuming f
By reducing the amount of bits of resolution, the output signal period can be reduced. For example, the
period can be as fast as 204.8 µs (4882 Hz) with 12 bits of resolution, as fast as 12.8 µs (78.125 KHz) with
eight bits of resolution, and as fast as 3.2 µs (312.5 KHz) with six bits of resolution (still assuming a f
= 40 MHz and the MCPSM set to divide by two).
The MPWMSM is composed of:
17-48
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PWM period and pulse width values provided by software:
— Double-buffered for glitch-free period and pulse width changes
— Minimum output period/pulse-width increment: 50 ns (assuming f
— Maximum 50% duty-cycle output frequency: 10 MHz (assuming f
— Up to 16 bits of resolution for the output pulse width
— Wide range of periods
— Wide range of frequencies
Programmable duty cycle from 0% to 100%
Possible interrupt generation at start of every period
Software selectable output pulse polarity
Software readable output signal status
Possible use of signal as I/O port when PWM function is not needed
– 16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to 6.71 s (with 102.4 µs
– Eight bits of resolution: period range from 12.8 µs (with 50-ns steps) to 26.2 ms (with
– Maximum output frequency at f
– Minimum output frequency at f
– Maximum output frequency at f
– Minimum output frequency at f
steps)
102.4-µs steps)
prescaler selection: 305 Hz (3.27 ms.)
prescaler selection: 0.15 Hz (6.7 s.)
prescaler selection: 78125 Hz (12.8 µs.)
prescaler selection: 38.15 Hz (26.2 ms.)
MPC561/MPC563 Reference Manual, Rev. 1.2
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= 40 MHz with 16 bits of resolution and divide-by-4096
= 40 MHz with 8 bits of resolution and divide-by-4096
= 40 MHz with 16 bits of resolution and divide-by-2
= 40 MHz with 8 bits of resolution and divide-by-2
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= 40 MHz, the finest output pulse width
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= 40 MHz).
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= 40 MHz)
= 40 MHz)
Freescale Semiconductor
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