MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 787

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

A value must be written to the MPWMCNTR (which writes the same value into the MPWMPERR) and a
pulse width value written to MPWMPULR, before the MPWMSCR is written to. The latter access
initializes the clock prescaler.
17.10.6 MPWMSM Registers
The privilege level to access to the MPWMSM registers depends on the MIOS14MCR[SUPV]. The
privilege level is unrestricted after reset and can be change to supervisor by software.
17.10.6.1 MPWMSM Registers Organization
The MPWMSM register map comprises four 16-bit register locations, as shown in
bits return zero when read by the software. All register addresses in this section are specified as offsets
from the base address of the MPWMSM.
Freescale Semiconductor
0x30 600C
0x30 6000
0x30 6002
0x30 6004
0x30 6006
0x30 6008
0x30 600A
0x30 600E
0x30 6010
0x30 6012
0x30 6014
0x30 6016
0x30 6018
0x30 601A
Address
MPWMSM0 Period Register (MPWMPERR)
See
MPWMSM0 Pulse Register (MPWMPULR)
See
MPWMSM0 Count Register (MPWMCNTR)
See
MPWMSM0 Status/Control Register (MPWMSCR)
See
MPWMSM1 Period Register (MPWMPERR)
MPWMSM1 Pulse Register (MPWMPULR)
MPWMSM1 Count Register (MPWMCNTR)
MPWMSM1 Status/Control Register (MPWMSCR)
MPWMSM2 Period Register (MPWMPERR)
MPWMSM2 Pulse Register (MPWMPULR)
MPWMSM2 Count Register (MPWMCNTR)
MPWMSM2 Status/Control Register (MPWMSCR)
MPWMSM3 Period Register (MPWMPERR)
MPWMSM3 Pulse Register (MPWMPULR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-26
Table 17-27
Table 17-28
Table 17-29
Table 17-25. MPWMSM Address Map
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
MPWMSM0
MPWMSM1
MPWMSM2
MPWMSM3
Register
Modular Input/Output Subsystem (MIOS14)
Table
17-25. All unused
17-55