MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 317

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
buclk_enable = (STBUC | LOC) and LME lock indicates loss of lock status
bit (LOCS) for all cases and loss of clock sticky bit (LOCSS) when state 3
is active. When buclk_enable is changed, the chip asserts HRESET to
switch the system clock to BUCLK or PLL.
At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit
(LOCSS) is asserted, and the chip should operate with BUCLK.
buclk_enable = 1
& hreset_b = 0
else
3,BUCLK
6,BULCK
Figure 8-8. Clock Source Switching Flow Chart
MPC561/MPC563 Reference Manual, Rev. 1.2
poreset_b = 1
LME = 1
buclk_enable=0
& hreset_b=0
buclk_enable = 1
& hreset_b = 0
1,BUCLK
2,BUCLK
NOTE
else
5, osc
4, osc
LME = 0
buclk_enable = 0
& hreset_b = 0
hreset_b = 0
else
LOCS=0
Clocks and Power Control
8-15