MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 795

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

17.11.8.2 MPIOSM Data Direction Register (MPIOSMDDR)
17.12 MIOS14 Interrupts
This section describes the interrupt functions of the MIOS14 and its submodules and how these interrupts
are passed to the CPU via the peripheral bus. Interrupt requests from the MIOS14 are treated as exceptions
by the CPU and are dealt with by the CPU’s exception processing routines. For a more detailed description
of exception processing in the relevant microprocessors, please refer
and to the RCPU Reference Manual.
17.12.1 MIOS14 Interrupt Structure
The MIOS14 and its submodules are capable of generating interrupts on different levels to be transmitted
to the CPU via the peripheral bus. Inside the MIOS14, all the information required for requesting and
servicing the interrupts are treated in two different sections:
The MIRSM gathers in service request flags from each group of up to 16 submodules and transfers those
requests to the MIOS14 interrupt control section (ICS).
interrupt architecture.
Freescale Semiconductor
•
•
SRESET
Bits
15:0
Bits
0:15
The interrupt request submodules (MIRSM)
The interrupt control section (ICS) of the MBISM
Field DDR
Addr
DDR15–
DDR0
DATA15–
DATA0
MSB
Name
Name
15
0
DDR
14
1
These bits are read/write data bits that define the data direction status for each implemented I/O
signal of the MPIOSM
0 = corresponding signal is input.
1 = corresponding signal is output.
Figure 17-33. MPIOSM Data Direction Register (MPIOSMDDR)
These bits are read/write data bits that define the value to be driven to the pad in output mode,
for each implemented I/O signal of the MPIOSM. The Msb is 15, Lsb is 0.
DDR
13
2
DDR
12
3
Table 17-34. MPIOSMDDR Bit Descriptions
Table 17-33. MPIOSMDR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
DDR
11
4
DDR
10
5
DDR
0000_0000_0000_0000
9
6
DDR
0x30 6100
8
7
Figure 17-34
Description
Description
DDR
7
8
DDR
6
9
Chapter 3, “Central Processing
DDR
shows a block diagram of the whole
10
5
Modular Input/Output Subsystem (MIOS14)
DDR
11
4
DDR
12
3
DDR
13
2
DDR
14
1
DDR
15
0
Unit”
17-63