MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 943
![](/photos/31/37/313722/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 943 of 1420
- Download datasheet (11Mb)
23.4.2
The development serial clock (DSCK) is used to shift data into and out of the development port shift
register. At the same time, the new most significant bit of the shift register is presented at the DSDO pin.
In all further discussions references to the DSCK signal imply the internal synchronized value of the clock.
The DSCK input must be driven either high or low at all times and not allowed to float. A typical target
environment would pull this input low with a resistor.
The clock may be implemented as a free running clock or as gated clock. As discussed in section
Section 23.4.6.5, “Development Port Serial Communications — Trap Enable
Section 23.4.6.8, “Development Port Serial Communications — Debug
controlled by ready and start signals so the clock does not need to be gated with the serial transmissions.
The DSCK pin is also used at reset to enable debug mode and immediately following reset to optionally
cause immediate entry into debug mode following reset.
23.4.3
Data to be transferred into the development port shift register is presented at the development serial data
in (DSDI) pin by external logic. To be sure that the correct value is used internally. When driven
asynchronous (synchronous) with the system clock, the data presented to DSDI must be stable a setup time
before the rising edge of DSCK (CLKOUT) and a hold time after the rising edge of DSCK (CLKOUT).
The DSDI pin is also used at reset to control the overall chip configuration mode and to determine the
development port clock mode. See section
— Clock Mode
23.4.4
The debug mode logic shifts data out of the development port shift register using the development serial
data out (DSDO) pin. All transitions on DSDO are synchronous with DSCK or CLKOUT depending on
the clock mode. Data will be valid a setup time before the rising edge of the clock and will remain valid a
hold time after the rising edge of the clock.
Refer to
23.4.5
The freeze indication means that the processor is in debug mode (i.e., normal processor execution of user
code is frozen). On the MPC561/MPC563, the freeze state can be indicated by three different pins. The
FRZ signal is generated synchronously with the system clock. This indication may be used to halt any
off-chip device while in debug mode as well as a handshake means between the debug tool and the debug
port. The internal freeze status can also be monitored through status in the data shifted out of the debug
port.
Freescale Semiconductor
Table 23-12
Development Serial Clock
Development Serial Data In
Development Serial Data Out
Freeze Signal
Selection” for more information.
for DSDO data meaning.
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.4.6.4, “Development Port Serial Communications
Mode,” the shifting of data is
Mode” and section
Development Support
23-29
Related parts for MPC561MZP56
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![1623776-3](/images/manufacturer_photos/0/6/654/te_connectivity_tmb.jpg)
Part Number:
Description:
MPC5 1K0 5%
Manufacturer:
TE Connectivity
Datasheet:
![MPC52501J](/photos/26/31/263125/42254495_tmb.jpg)
Part Number:
Description:
MPC5 500R 5%
Manufacturer:
TE Connectivity
Datasheet:
![1-1623776-7](/images/manufacturer_photos/0/6/687/tyco_electronics_tmb.jpg)
Part Number:
Description:
MPC5 5K0 5%
Manufacturer:
Tyco Electronics
Datasheet:
![1-1623776-9](/images/manufacturer_photos/0/6/687/tyco_electronics_tmb.jpg)
Part Number:
Description:
MPC5 5R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
![1-1623776-8](/images/manufacturer_photos/0/6/687/tyco_electronics_tmb.jpg)
Part Number:
Description:
MPC5 50K 5%
Manufacturer:
Tyco Electronics
Datasheet:
![1623776-6](/images/manufacturer_photos/0/6/687/tyco_electronics_tmb.jpg)
Part Number:
Description:
MPC5 1R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
![TWR-ELEV](/photos/9/0/90062/twr-elev_inside_tmb.jpg)
Part Number:
Description:
TOWER ELEVATOR BOARDS HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-SER](/photos/9/0/90065/twr-ser_tmb.jpg)
Part Number:
Description:
TOWER SERIAL I/O HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-LCD](/photos/37/59/375952/twr-lcd_bd_tmb.jpg)
Part Number:
Description:
LCD MODULE FOR TWR SYSTEM
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMX51LCD](/photos/37/58/375843/mx51-lcd_tmb.jpg)
Part Number:
Description:
DAUGHTER LCD WVGA I.MX51
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-MPC5125](/photos/37/59/375933/twrmpc5125_tmb.jpg)
Part Number:
Description:
TOWER SYSTEM BOARD MPC5125
Manufacturer:
Freescale Semiconductor
Datasheet: