MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1419

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Transmitter Enable (TE) 15-46
Transmitter enable (TE) 15-48
TRE 23-44
Trigger
TS signal 9-5
TSIZ[0:1] 9-4
TSIZ0 9-1
TSIZ1 9-1
TSM D-7
T
TSYNC 16-29
TX/RX 16-34
TXECTR 16-36
TXMODE 16-28
TXWARN 16-34
U
UART D-12
UBA 24-12
UC3F
UC3FCFIG register 21-16
UC3FCTL register 21-11
UC3FMCR register 21-5
UC3FMCRE register 21-8
UDI 24-15
UIMB interface
UIMB module configuration register 12-7
UIPEND register 12-8
UMCR register 12-7
Universal asynchronous receiver/transmitter
Freescale Semiconductor
SR
data
error status flag (TXWARN) 16-34
interrupt enable (TIE) 15-47
pin configuration control (TXMODE) 16-28
RAM 15-23
event 13-28
overrun error (TOR) 13-55
512-Kbyte array 21-19
array addressing 21-15
censorship states 21-30
features 21-3
high voltage operations 21-21
operation 21-19
program sequencing 21-22
registers 21-5
shadow row 21-15
signals 21-4
features 12-1
bit (TC) 15-49
interrupt enable (TCIE) 15-47
register empty (TDRE) flag 15-49
(UART) D-12
13-9
,
14-8
,
,
,
9-37
13-54
9-38
,
14-29
,
14-53
,
14-54
,
,
15-54
15-55
MPC561/MPC563 Reference Manual, Rev. 1.2
Unordered exceptions 3-35
User Instruction Set Architecture
User Instruction Set Architecture (Book 1)
user-mapped registers
Using the TPU Function Library and TPU Emulation
UX bit 3-14
V
V
V
VDDSYN 8-22
VE bit 3-15
Vector table, exception 3-36
Vector table, exceptions 3-36
VFLSn 23-30
VFn 23-2
V
V
Virtual Environment Architecture (Book 2)
Virtual Environment Architecture (VEA) 3-43
Voltage
V
V
V
VSRMCR 8-37
VSS 8-23
V
VSSSYN 8-22
VX bit 3-14
CF
DDA
IH
IL
RH
RL
SRC
SSA
parameters
Book 1
branch instructions, 3-40
branch processor, 3-40
computation modes, 3-39
exceptions, 3-40
fixed point-processor, 3-41
floating point processor, 3-41
instruction classes, 3-40
load/store processor, 3-42
reserved fields, 3-39
READI 24-8
operand placement effects, 3-43
storage control instructions, 3-43
timebase register 3-44
inputs 13-66
reference pins 13-71
receiver parameters D-13
transmitter parameters D-12
instruction fetching, 3-40
Mode 19-5
14-69
14-73
13-66
13-66
13-75
13-31
13-31
13-75
13-67
13-67
,
,
,
,
,
,
14-70
14-65
14-65
14-73
13-36
,
,
13-32
,
14-73
13-71
13-71
,
14-65
,
,
14-73
,
13-71
,
13-36
,
14-66
14-66
,
14-69
,
,
13-75
,
13-71
,
14-70
14-70
,
,
14-37
13-75
,
,
14-69
14-34
,
,
14-70
14-37
Index-19
,
,