MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 351

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

9.5.2.2
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed
transaction protocol.
Freescale Semiconductor
CLKOUT
BR
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
Data
TA
Single Beat Write Flow
Figure 9-6. Single Beat Read Cycle – Basic Timing – One Wait State
O
O
MPC561/MPC563 Reference Manual, Rev. 1.2
Receive bus grant and bus busy negated
O
O
assert BB, drive address and assert TS
Wait state
Data is valid
External Bus Interface
9-11