MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 702

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
Table 16-7
“Programming
16.3.3
The TouCAN module uses three 8-bit registers to set up the bit timing parameters required by the CAN
protocol. Control registers one and two (CANCTRL1, CANCTRL2) contain the PROPSEG, PSEG1,
PSEG2, and the RJW fields that allow configuration of the bit timing parameters. The prescaler divide
register (PRESDIV) allows selection of the ratio used to derive the serial clock (S-clock) from the system
clock. The time quanta clock operates at the S-clock frequency.
clock, CAN bit rate, and S-clock bit timing parameters, and
16-8
Mask Bit
1
2
3
4
5
6
7
Message Buffer (MB)/Mask
Match for extended format (MB3).
Match for standard format (MB2).
No match for MB3 because of ID0.
No match for MB2 because of ID28.
No match for MB3 because of ID28, match for MB14.
No match for MB14 because of ID27.
Match for MB14.
shows mask examples for normal and extended messages. Refer to
0
1
Bit Timing
Model” for more information on Rx mask registers.
Rx Global Mask
Rx Message In
Rx Message In
Rx 14 Mask
The corresponding incoming ID bit is “don’t care”
The corresponding ID bit is checked against the incoming ID bit to see if a match exists
MB14
MB2
MB3
MB4
MB5
Table 16-7. Mask Examples for Normal/Extended Messages
Table 16-6. Receive Mask Register Bit Values
MPC561/MPC563 Reference Manual, Rev. 1.2
1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 1 1 1 0 1
1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 1 1 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0
0 1 1 1 1 1 1 1 0 0 0
0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 0 0 0
0 1 1 1 1 1 1 1 0 0 0
ID[28:18]
Base ID
Values
IDE
0
1
0
1
1
1
0
1
0
1
1
1
Figure 16-5
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 16-8
Extended ID
ID[17:0]
shows the relationship between
—
—
—
—
provides examples of system
Section 16.7,
Freescale Semiconductor
Match
—
14
—
—
—
—
—
—
—
—
—
3
2
—
1
2
3
4
5
6
7