MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 265
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.2.2.1.1
The SIUMCR contains bits which configure various features in the SIU module. The register contents are
shown below.
Freescale Semiconductor
1
9:10
Bits
HRESET ID0
HRESET
1:3
4:7
The reset value is a reset configuration word value, extracted from the internal data bus line. Refer to
11
12
0
8
Reset Configuration Word
Field EARB
Field
Addr
DSHW
DBGC
ATWC
Name
EARB
EARP
DBPC
MSB
SIU Module Configuration Register (SIUMCR)
All SIUMCR fields which are controlled by the reset configuration word
should not be changed by software while the corresponding functions are
active.
—
16
0
0
—
1
ID[17:18]
17
1
SC
External arbitration
0 Internal arbitration is performed
1 External arbitration is assumed
External arbitration request priority. This field defines the priority of an external master’s
arbitration request. This field is valid when EARB is cleared. Refer to
Bus
Reserved
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and Flash EEPROM). This field is locked by the DLK bit. Note that
instruction show cycles are programmed in the ICTRL and L-bus data show cycles are
programmed in the L2UMCR.
0 Disable show cycles for all internal data cycles
1 Show address and data of all internal data cycles
Debug pins configuration. Refer to
Reserved.
Address write type enable configuration. This bit configures the pins to function as byte write
enables or address types for debugging purposes.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
EARP
Figure 6-12. SIU Module Configuration Register (SIUMCR)
18
2
Arbiter,” for details.
1
(RCW).”
RCTX MLRC
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
000_0000_0
Table 6-7. SIUMCR Bit Descriptions
20
4
21
5
—
22 23
6
—
WARNING
7
DSHW
MTSC NOS
0x2F C000
24
Table
8
0_0000_0000_0000
6-8.
HOW EICEN
Description
25
9
ID[9:10]
DBGC
10
26
1
1
LPMASK
ID11
_EN
—
11
27
System Configuration and Protection
1
Section 9.5.7.4, “Internal
BURST
ATWC
ID12
_EN
12
28
1
Section 7.5.2, “Hard
13
29
GPC
000
14
30
—
DLK
LSB
15
31
6-25
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