MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 165

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Bits
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
FE0
FE1
ILE
ME
EE
PR
SE
BE
FP
—
—
IP
IR
Table 3-11. Machine State Register Bit Descriptions (continued)
Reserved
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception. Little-endian mode is not
supported on the MPC561/MPC563. This bit should be cleared to 0 at all times.
0 The processor runs in big-endian mode during exception processing.
1 The processor runs in little-endian mode during exception processing.
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts (EE = 0) in the RCPU before clearing or masking any
interrupt source from the USIU or external pins. For external interrupts, it is recommended that
the edge-triggered interrupt scheme be used. See
Controller.”
0 The processor delays recognition of external interrupts and decrementer exception
1 The processor is enabled to take an external interrupt or the decrementer exception.
Privilege level.
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
Floating-point available.
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
1 The processor can execute floating-point instructions, and can take floating-point enabled
Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
Floating-point exception mode 0 (See
Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
Floating-point exception mode 1 (See
Reserved
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
Instruction relocation.
0 Instruction address translation is off; the BBC IMPU does not check for address permission
1 Instruction address translation is on; the BBC IMPU checks for address permission
conditions.
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
exception type program exceptions.
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception.
attributes.
attributes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
Table
Description
3-12.)
3-12).
Section 6.1.4, “Enhanced Interrupt
Central Processing Unit
3-21