MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 54
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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liv
Figure
Number
Development Port Data Register (DPDR) ............................................................................ 23-53
READI Functional Block Diagram......................................................................................... 24-3
READI Ownership Trace Register (OTR).............................................................................. 24-9
READI Device ID Register .................................................................................................. 24-10
READI Development Control (DC) Register ....................................................................... 24-10
READI Mode Control (MC) Register .................................................................................. 24-12
READI User Base Address Register .................................................................................... 24-13
READI Read/Write Access Register .................................................................................... 24-14
READI Upload/Download Information Register ................................................................. 24-16
RWD Field Configuration .................................................................................................... 24-17
READI Data Trace Attributes 1 Register (DTA1)
READI Data Trace Attributes 2 Register (DTA2) ............................................................... 24-17
Functional Diagram of Signal Interface................................................................................ 24-22
Auxiliary Signal Packet Structure for Program Trace Indirect
Branch Message .................................................................................................................... 24-23
MSEI/MSEO Transfers......................................................................................................... 24-24
Transmission Sequence of Messages.................................................................................... 24-32
READI Module Enabled....................................................................................................... 24-34
Enabling Program Trace Out of System Reset ..................................................................... 24-36
READI Mode Selection ........................................................................................................ 24-36
READI Module Disabled...................................................................................................... 24-37
Direct Branch Message Format ............................................................................................ 24-38
Indirect Branch Message Format .......................................................................................... 24-39
Indirect Branch Message Format with Compressed Code.................................................... 24-39
Bit Pointer Format with Compressed Code .......................................................................... 24-39
Program Trace Correction Message Format ......................................................................... 24-42
Direct Branch Synchronization Message Format (PTSM = 0)............................................. 24-44
Direct Branch Synchronization Message Format (PTSM = 1)............................................. 24-44
Indirect Branch Synchronization Message Format (PTSM = 0) .......................................... 24-44
Indirect Branch Synchronization Message Format (PTSM = 1) .......................................... 24-44
Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 0).................................................................................................................. 24-45
Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
Indirect Branch Synchronization Message Format with Compressed
Code (PTSM - 0)................................................................................................................... 24-45
Indirect Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
Program Trace Full Message Format.................................................................................... 24-46
Relative Address Generation and Re-Creation ..................................................................... 24-47
MPC561/MPC563 Reference Manual, Rev. 1.2
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