MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 619
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Chapter 15
Queued Serial Multi-Channel Module
The MPC561/MPC563 contains one queued serial multi-channel module (QSMCM). The QSMCM
provides three serial communication interfaces: the queued serial peripheral interface (QSPI) and two
serial communications interfaces (SCI/UART). These submodules communicate with the CPU via a
common slave bus interface unit (SBIU).
The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other
MCUs. It is enhanced from the original SPI in the QSMCM (queued serial module) to include a total of
160 bytes of queue RAM to accommodate more receive, transmit, and control information.
The duplicate, independent SCIs are full-duplex universal asynchronous receiver transmitter (UART)
serial interface. The original QSM SCI is enhanced by the addition of an SCI, a common external baud
clock source, receive and transmit buffers on one SCI. The SCIs are fully compatible with the SCI systems
found on other Freescale MCUs. The dual, independent SCI, DSCI, submodule is used to communicate
with external devices and other MCUs via an asynchronous serial bus. The DSCI has all of the capabilities
of previous SCI systems as well as several significant new features. The following paragraphs describe the
features, pins, programming model (memory map), registers, and the transmit and receive operations of
the DSCI.
The SBIU provides an interface between the QSMCM module and the intermodule bus (IMB3).
15.1
Block Diagram
Figure 15-1
shows the major components of the QSMCM.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-1
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