MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 876
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CDR3 Flash (UC3F) EEPROM
21-14
Bits
30
31
PEGOOD
Name
SES
EHV
EHV
HVS
SES
Start-end program or erase sequence. The SES bit is write protected by the STOP, HVS, and
EHV bits. The SES bit is used to signal the start and end of a program or erase sequence. At
the start of a program or erase sequence, SES is set. This will lock STOP, PROTECT,
SBPROTECT, BLOCK, SBBLOCK, SBEN, CSC, and PE. If PE = 0 and SES = 1, SIE will be write
locked. At this point, the UC3F EEPROM is ready to receive either the programming writes or
the erase interlock write.
NOTE: The erase interlock write is a write to any UC3F EEPROM array location after SES is set
and PE = 1.
If PE = 0 and SES = 1, writes to the UC3F array are programming writes. The first programming
write sets the address of the location to be programmed, and the data written is captured into
the program data latch for programming into the UC3F array. All programming writes after the
first programming write update the program data latch but do not change the address to be
programmed.
At the end of the program or erase operation, the SES bit must be cleared to return to normal
operation and release the STOP, PROTECT, SBPROTECT, BLOCK, SBBLOCK, CSC, SBEN,
and PE bits.
0 UC3F EEPROM not configured for program or erase operation
1 Configure UC3F EEPROM for program or erase operation
Enable high voltage. EHV can be asserted only after the SES bit has been asserted and a valid
programming write(s) or erase hardware interlock write has occurred. If an attempt is made to
assert EHV when SES is negated, or if a valid programming write or erase hardware interlock
write has not occurred since SES was asserted, EHV will remain negated.
The external program or erase enable pin (EPEE) and EHV are used to control the application
of the program or erase voltage to the UC3F EEPROM module. High voltage operations to the
UC3F EEPROM array, special shadow locations or FLASH NVM registers can occur only if
EHV = 1 and EPEE = 1.
Only after the correct hardware and software interlocks have been applied to the UC3F
EEPROM can EHV be set. Once EHV is set, SES cannot be changed and attempts to read the
array will not be acknowledged.
Clearing EHV during a program or erase operation will safely terminate the high voltage
operation. If EHV is cleared while using the embedded hardware program/erase algorithm, the
program/erase routine will abort the operation and exit normally.
0 Program or erase pulse disabled
1 Program or erase pulse enabled
Table 21-5. UC3FCTL Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 21-5. PEGOOD Valid Time
Valid Time
PEGOOD
Description
Valid Time
PEGOOD
Freescale Semiconductor
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