MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 544
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
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QADC64E Enhanced Mode Operation
14.2
This section gives an overview of the implementation of the two QADC64E modules on the
MPC561/MPC563. It can also be used for a quick reference while programming the modules.
14.2.1
The analog section includes input signals, an analog multiplexer, and the sample and hold circuits. The
analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a
high-gain comparator.
The digital control section contains queue control logic to sequence the conversion process and interrupt
generation logic. Also included are the periodic/interval timer, control and status registers, the conversion
command word (CCW) table RAM, and the result table RAM.
The bus interface unit (BIU) allows the QADC64E to operate with the applications software through the
IMB3 environment.
14-2
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Internal sample and hold
Directly supports up to four external multiplexers (for example, the MC14051)
Up to 41 analog input channels using QADC64 external multiplexing
Programmable input sample time for various source impedances
Minimum conversion time of 7µs (with typical QCLK frequency, 2 MHz)
Two conversion command queues with a total of 64 entries
Sub-queues possible using pause mechanism
Queue complete and pause software interrupts available on both queues
Queue pointers indicate current location for each queue
Automated queue modes initiated by
— External edge trigger
— Periodic/Interval timer, within QADC64E module
— Software command
— External gated trigger (queue 1 only)
Single-scan or continuous-scan of queues
64 result registers in each QADC64E module
Output readable in three formats
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
Unused analog channels can be used as digital input/output signals
Modulus prescaler can divide the system clock for the converter by two to 128
Alternate reference input, with control in the conversion command word (CCW)
Key Features and Quick Reference Diagrams
Features of the QADC64E Enhanced Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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