MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 449
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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For these registers a bus cycle will be performed on the L-bus and the U-bus with the address as shown in
Table
11.8.1
The L2U registers are accessible from the U-bus side only if it is a supervisor mode data access and the
register address is correct and it is indicated on the U-bus that it is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the U-bus side will cause a
data error on the U-bus.
11.8.2
All L2U registers are defined by MPC500 architecture as being 32-bit registers in normal mode. There is
no MPC500 instruction to access either a half word or a byte of the special purpose register.
All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access
in peripheral mode will result in a word transaction.
11.8.3
The L2U module configuration register (L2U_MCR) is used to control the L2U module operation.
Freescale Semiconductor
.
1
L2U_GRA
L2U_RA2
L2U_RA3
When EMCR[CONT] = 0, for external master access only.
11-6.
Name
U-Bus Access
Transaction Size
L2U Module Configuration Register (L2U_MCR)
SPR #
826
827
536
SPR[5:9]
11001
11001
10000
Table 11-5. L2U (PPC) Register Decode (continued)
A[0:17]
Table 11-6. Hex Address For SPR Cycles
MPC561/MPC563 Reference Manual, Rev. 1.2
0
SPR[0:4]
11010
11011
11000
External Master
A[18:22]
spr[5:9]
0x0000_3590
0x0000_3790
0x0000_3100
Address for
Access
1
A[23:27]
spr[0:4]
Access
SUPR
SUPR
SUPR
A[28:31]
0
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
L-Bus to U-Bus Interface (L2U)
Description
11-13
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