MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 160

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
Table 3-6
3.7.4
The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a
mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields: CR0 to CR7.
The CR fields can be set in the following ways:
3-16
•
•
•
•
•
30–31
Bits
Reset
29
Field
Specified fields of the CR can be set by an instruction (mtcrf) to move to the CR from a GPR.
Specified fields of the CR can be moved from one CRx field to another with the mcrf instruction.
A specified field of the CR can be set by an instruction (mcrxr) to move to the CR from the XER.
Condition register logical instructions can be used to perform logical operations on specified bits
in the condition register.
CR0 can be the implicit result of an integer operation.
illustrates the floating-point result flags that correspond to FPSCR[15:19].
Condition Register (CR)
MSB
0
Name
RN
CR0
NI
1
2
3
Non-IEEE mode bit.
Floating-point rounding control.
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward -infinity
4
CR1
5
Table 3-6. Floating-Point Result Flags in FPSCR
6
Table 3-5. FPSCR Bit Descriptions (continued)
7
MPC561/MPC563 Reference Manual, Rev. 1.2
Result Flags
8
(Bits 15:19)
Figure 3-7. Condition Register (CR)
C<>=?
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
10001
01001
01000
11000
10010
00010
10100
00100
00101
CR2
CR3
+ Denormalized number
– Denormalized number
– Normalized number
+ Normalized number
Result Value Class
Unchanged
Quiet NaN
Description
– Infinity
+ Infinity
+ Zero
– Zero
CR4
CR5
CR6
Freescale Semiconductor
—
—
CR7
LSB
31