MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 785

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

32 µs/1280 0.476 0.953 1.907 3.814 7.629 15.24 30.51 61.03
64 µs/2560 0.238 0.476 0.953 1.907 3.814 7.629 15.24 30.51 61.03
96 µs/3840 0.159 0.318 0.636 1.271 2.543 5.086 10.17 20.34 40.69 81.38 162.
Minimum
25.6 µs
38.4 µs
44.8 µs
51.2 µs
57.6 µs
70.4 µs
76.8 µs
83.2 µs
89.6 µs
17.10.3.7 MPWMSM Status and Control Register (SCR)
One register is used to initialize the MPWMSM and monitor its operation. Control bits are included to
allow the software to enable the PWM generator, establish the output signal polarity, select the counter
clock rate and set the glitch-free mode. A status bit is included to allow the software to read the state of
the output signal.
17.10.3.8 MPWMSM Interrupt
A valid MPWMSM interrupt is recognized when a pulse occurs on the flag line to set the flag bit and the
interrupt enable bit is set for the corresponding level in the MIRSM (Refer to
Interrupts,”
Request Submodule
every period.
Freescale Semiconductor
Width
Pulse
/1024
/1536
/1792
/2048
/2304
/2816
/3072
/3328
/3584
Table 17-24. PWM Pulse/Frequency Ranges (in Hz) Using /1 or /256 Option (40 MHz) (continued)
0.596 1.192 2.384 4.768 9.536 19.07 38.14 76.29 152.5 305.1 610.
0.397 0.795 1.589 3.179 6.358 12.71 25.43 50.86 101.7 203.5 406.
0.298 0.596 1.192 2.384 4.768 9.536 19.07 38.14 76.29 152.5 305.
0.264 0.529 1.059 2.119 4.238 8.477 16.95 33.90 67.81 135.6 271.
0.216 0.433 0.867 1.734 3.468 6.936 13.87 27.74 55.48 110.9 221.
0.198 0.397 0.795 1.589 3.179 6.358 12.71 25.43 50.86 101.7 203.
0.183 0.366 0.733 1.467 2.934 5.869 11.74 23.47 46.95
0.170 0.340 0.681 1.362 2.724 5.449 10.89 21.80 43.59 87.19 174.
0.34 0.681 1.362 2.724 5.449 10.89 21.80 43.59 87.19 174.4 348.
16
Section 17.12.1, “MIOS14 Interrupt
15
(MIRSM)” for details about interrupts). A set flag pulse is generated at the start of
14
13
MPC561/MPC563 Reference Manual, Rev. 1.2
12
11
10
Structure” and
Bits of Resolution
9
122
8
Section 17.12.2, “MIOS14 Interrupt
244.1 488.
93.9
122
7
244.
187.
Modular Input/Output Subsystem (MIOS14)
3
2
9
8
1
2
1
9
5
8
4
8
6
1220
976.
813.
697.
610.
542.
488.
443.
406.
375.
348.
325.
Section 17.12, “MIOS14
5
5
8
5
3
5
2
9
9
6
8
5
976.5
887.8
813.8
751.2
697.5
2441
1953
1627
1395
1220
1085
651
4
1953
1775
1627
1502
1395
4882
3906
3255
2790
2441
2170
1302
3
9765
7812
6510
5580
4882
4340
3906
3551
3255
3004
2790
2604
2
17-53
19.5K
15.6K
11.1K
9765
8680
7812
7102
6510
6009
5580
5208
13K
1