MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 45
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Figure
Number
4 Beat Burst Read with Short Setup Time (Zero Wait State) ............................................... 10-10
GPCM–Memory Devices Interface ...................................................................................... 10-12
Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)....................................... 10-13
Peripheral Devices Interface ................................................................................................. 10-13
Peripheral Devices Basic Timing (ACS = 11, TRLX = 0) ................................................... 10-14
Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1).................................... 10-15
Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ................ 10-16
Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ................ 10-17
Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1.................. 10-18
Consecutive Accesses (Write After Read, EHTR = 0) ......................................................... 10-19
Consecutive Accesses (Write After Read, EHTR = 1) ......................................................... 10-20
Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) .......................................................... 10-21
Consecutive Accesses (Read After Read from Same Bank, EHTR = 1).............................. 10-22
Aliasing Phenomenon Illustration ........................................................................................ 10-26
Synchronous External Master
Configuration for GPCM-Handled Memory Devices .......................................................... 10-29
Synchronous External Master Basic Access (GPCM Controlled)........................................ 10-30
Memory Controller Status Register (MSTAT) ..................................................................... 10-32
Memory Controller Base Registers 0–3 (BR0–BR3) ........................................................... 10-32
Memory Controller Option Registers 1–3 (OR0–OR3) ....................................................... 10-34
Dual-Mapping Base Register (DMBR) ................................................................................ 10-36
Dual-Mapping Option Register (DMOR)............................................................................. 10-37
L2U Bus Interface Block Diagram ......................................................................................... 11-3
DMPU Basic Functional Diagram .......................................................................................... 11-5
Region Base Address Example............................................................................................... 11-7
L2U Module Configuration Register (L2U_MCR) .............................................................. 11-14
L2U Region x Base Address Register (L2U_RBAx) ........................................................... 11-14
L2U Region X Attribute Register (L2U_RAx) .................................................................... 11-15
L2U Global Region Attribute Register (L2U_GRA) ........................................................... 11-16
UIMB Interface Module Block Diagram................................................................................ 12-2
IMB3 Clock – Full-Speed IMB3 Bus ..................................................................................... 12-3
IMB3 Clock – Half-Speed IMB3 Bus .................................................................................... 12-3
Interrupt Synchronizer Signal Flow........................................................................................ 12-4
Time-Multiplexing Protocol for IRQ Signals ......................................................................... 12-5
Interrupt Synchronizer Block Diagram................................................................................... 12-6
UIMB Module Configuration Register (UMCR) ................................................................... 12-7
Pending Interrupt Request Register (UIPEND)...................................................................... 12-9
QADC64E Block Diagram ..................................................................................................... 13-1
QADC64E Conversion Queue Operation............................................................................... 13-5
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
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