MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 639

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

15.6.1.5
The SPSR contains information concerning the current serial transmission. Only the QSPI can set bits in
this register. To clear status flags, the CPU reads SPSR with the flags set and then writes the SPSR with
zeros in the appropriate bits. Writes to CPTQP have no effect.
Freescale Semiconductor
Note: See bit descriptions in
SRESET
1
2
See bit descriptions in
SPSR can be accessed as an 8-bit register at location 0x30 501F or 0x30 541F.
Bits
8:15
SRESET
0:4
5
6
7
Field
Addr
Field
Addr
MSB
LOOPQ
QSPI Status Register (SPSR)
0
Name
SPSR
HMIE
HALT
MSB
—
0
1
1
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 Feedback path disabled.
1 Feedback path enabled.
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 HALTA and MODF interrupts disabled.
1 HALTA and MODF interrupts enabled.
from which it can later be restarted. Refer to
the
0 QSPI operates normally.
1 QSPI is halted for subsequent restart.
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
See
—
Table 15-17
2
SPI.”
2
Table 15-18
Table 15-18
3
Figure 15-14. SPCR3 — QSPI Control Register 3
SPCR3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 15-15. QSPI Status Register (SPSR)
Table 15-17. SPCR3 Bit Descriptions
4
4
1
for bit descriptions.
LOOPQ HMIE HALT
5
5
6
0000_0000_0000_0000
0000_0000_0000_0000
6
0x30 501E (SPSR)
7
0x30 501E
7
SPIF MODF HALTA
Description
8
Section 15.6.4.1, “Enabling, Disabling, and Halting
8
9
2
9
10
10
11
Queued Serial Multi-Channel Module
11
SPSR*
12
12
CPTQP
13
13
14
14
LSB
15
LSB
15
15-21