MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 471
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
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Table 13-4
multiplexer chips using one QADC module.
13.3
The QADC64E has three global registers for configuring module operation:
The global registers are always defined to be in supervisor-only data space. Refer to
QADC64E_A address map and
“Supervisor/Unrestricted Address
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
Freescale Semiconductor
I
•
•
•
•
•
•
Module configuration register
(QADMCR)”)
Interrupt register
Test register (QADCTEST) for factory tests.
Control register 0 (QACR0) contains hardware configuration information
“Control Register 0
Control register 1 (QACR1) is associated with queue 1
(QACR1)”)
Control register 2 (QACR2) is associated with queue 2
(QACR2)”)
Programming the QADC64E Registers
shows the total number of analog input channels supported with zero to four external
No External
If either QADC64E_A or QADC64E_B is in external multiplexing
(EMUX) mode then the multiplexer address signal channels, AN[52:54]
should not be programmed into queues.
MUX Chips
16
Multiplexed Analog Input
(Section 13.3.2, “QADC64E Interrupt Register
Directly Connected + External Multiplexed = Total Channels
(QACR0)”)
NOTE: QADC64E External MUX Users
ANw (AN[0])
ANx (AN[1])
ANy (AN[2])
ANz (AN[3])
Table 13-3. Multiplexed Analog Input Channels
One External
MUX Chip
Table 13-2
MPC561/MPC563 Reference Manual, Rev. 1.2
Number of Analog Input Channels Available
Space” for access modes of these registers.
20
Table 13-4. Analog Input Channels
(Section 13.3.1, “QADC64E Module Configuration Register
for the QADC64E_B address map. See
Two External
MUX Chips
27
16, 18, 20, 22, 24, 26, 28, 30
17, 19, 21, 23, 25, 27, 29, 31
0, 2, 4, 6, 8, 10, 12, 14
1, 3, 5, 7, 9, 11, 13, 15
Channels
Three External
(Section 13.3.6, “Control Register 1
(Section 13.3.7, “Control Register 2
MUX Chips
34
(QADCINT)”
QADC64E Legacy Mode Operation
Four External
MUX Chips
(Section 13.3.5,
Section 13.3.1.4,
41
Table 13-1
for the
13-7
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