MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 273
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.2.2.2.3
6.2.2.2.4
SIMASK is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND register.
SIMASK2 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND2 register.
SIMASK3 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND3 register.
When the bit is set, it enables the generation of an interrupt request to the RCPU. SIMASK, SIMASK2,
SIMASK3 are updated by software and cleared upon reset. It is the responsibility of the software to
determine which of the interrupt sources are enabled at a given time.
Freescale Semiconductor
SRESET
SRESET
Field
Field
Addr
IRQ20
MSB
IMB
16
0
SIU Interrupt Pending Register 3 (SIPEND3)
SIU Interrupt Mask Register (SIMASK)
Disable external interrupts in the core prior to changing any interrupt
controller related register (SIMASK, SIPEND, SIEL, or SISR). Refer to
MSR[EE] bit description in
handling of the EIC in
Operation.”
IRQ21
IMB
17
1
IRQ22
IMB
18
2
Figure 6-17. SIU Interrupt Pending Register 3 (SIPEND3)
IRQ23
IMB
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
IRQ
20
6
4
Section 6.1.4.4, “Enhanced Interrupt Controller
LVL
21
6
5
Table 3-11
IRQ24
IMB
22
6
0000_0000_0000_0000
0000_0000_0000_0000
NOTE
IRQ25
IMB
0x2F C044
23
7
and the note regarding special
—
IRQ26
IMB
24
8
IRQ27
IMB
25
9
IRQ
10
26
7
LVL
11
27
System Configuration and Protection
7
IRQ28
IMB
12
28
IRQ29
IMB
13
29
IRQ30
IMB
14
30
IRQ31
IMB
LSB
15
31
6-33
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