EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 129

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
February 2005
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a
[(a
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks.
two-multipliers adder.
Figure 4–37. Two-Multipliers Adder Mode Implementing Complex Multiply
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18
multipliers or two different sums of two sets of four 9
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications.
adder mode.
×
(a + jb)
d) + (b
18
18
×
×
18
(c + jd) = [(a
c)] using one adder, for data widths up to 18 bits. Two
18
×
c) – (b
A
C
B
D
A
D
B
C
×
18
18
18
18
18
18
18
18
d)] using one subtractor and the imaginary part
×
c) – (b
36
36
36
36
Figure 4–38
×
Stratix GX Device Handbook, Volume 1
d)] + j
Subtractor
Adder
DSP Block
×
Figure 4–37
[(a
shows the four multipliers
37
37
×
d) + (b
Stratix GX Architecture
(Imaginary Part)
(A × C) − (B × D)
(A × D) + (B × C)
(Real Part)
×
9-bit multipliers
shows an 18-bit
×
×
18-bit
c)]
4–63