EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 268

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

High-Speed I/O Specification
6–66
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
t
t
f
% spread
t
LSKEW
SKEW
SS
ARESET
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 3 of 3)
Symbol
The minimum input clock frequency to the PFD (f
See
t
This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
Actual jitter performance may vary based on the system configuration.
Total required time to reconfigure and lock is equal to t
changed, then t
The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected.
Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
Exact, user-controllable value depends on the PLL settings.
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
FCOMP
“Maximum Input & Output Clock Rates” on page
Tables 6–88
can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
Clock skew between two external clock
outputs driven by the same counter
Clock skew between two external clock
outputs driven by the different counters
with the same settings
Spread spectrum modulation frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
DLOCK
through 6–90:
is equal to 0.
Parameter
(9)
areset
IN
/N) must be at least 3 MHz for Stratix device enhanced PLLs.
Min
6–54.
0.5
30
DLOCK
10
±50
±75
+ t
Typ
CONFIG
. If only post-scale counters and delays are
Max
150
0.6
Altera Corporation
June 2006
Unit
kHz
ps
ps
ns
%