EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 143

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
February 2005
Notes to
(1)
(2)
(3)
EP1SGX10
EP1SGX25
EP1SGX40
Clock multiplication and division
Phase shift
Delay shift
Clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Table 4–17. Stratix GX Device PLL Availability
Table 4–18. Stratix GX Enhanced PLL & Fast PLL Features (Part 1 of 2)
Device
PLLs 3, 4, 9, and 10 are not available in Stratix GX devices. However, these PLLs are listed in
the Stratix GX PLL numbering scheme is consistent with Stratix devices.
PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
PLLs 11 and 12 each have one single-ended output.
Table
Feature
4–17:
v
v
v
1
v
v
v
2
clocking, programmable bandwidth, phase and delay control, and
dynamic PLL reconfiguration, the Stratix GX device’s enhanced PLLs
provide you with complete control of your clocks and system timing. The
fast PLLs provide general purpose clocking with multiplication and
phase shifting as well as high-speed outputs for high-speed differential
I/O support. Enhanced and fast PLLs work together with the Stratix GX
high-speed I/O and advanced clock architecture to provide significant
improvements in system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices.
available for each Stratix GX device and their type.
enhanced PLL and fast PLL features in Stratix GX devices.
3
(1)
Down to 156.25-ps increments (3),
4
m/ (n
Fast PLLs
250-ps increments for ±3 ns
(1)
×
Enhanced PLL
post-scale counter)
v
7
(4)
v
v
v
v
v
6
v
8
9
Table 4–17
(1)
(1)
Stratix GX Device Handbook, Volume 1
10
(1)
Down to 125-ps increments (3),
shows which PLLs are
Notes (1)–(8)
m/(post-scale counter)
5
v
v
v
(2)
Stratix GX Architecture
Enhanced PLLs
Table 4–18
6
Fast PLL
v
v
v
(2)
3
v
Table 4–17
(5)
11
v
(3)
shows the
because
(2)
12
v
4–77
(3)
(4)