EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 152

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

PLLs & Clock Networks
Figure 4–53. Dynamically Programmable Counters & Delays in Stratix GX Device Enhanced PLLs
4–86
Stratix GX Device Handbook, Volume 1
scandata
scanaclr
scanclk
f
REF
÷n
Counters and Clock
Delay Settings are
Programmable
Δt
PLL reconfiguration data is shifted into serial registers from the logic
array or external devices. The PLL input shift data uses a reference input
shift clock. Once the last bit of the serial chain is clocked in, the register
chain is synchronously loaded into the PLL configuration bits. The shift
circuitry also provides an asynchronous clear for the serial registers.
Programmable Bandwidth
You have advanced control of the PLL bandwidth using the
programmable control of the PLL loop characteristics, including loop
filter and charge pump. The PLL’s bandwidth is a measure of its ability to
track the input clock and jitter. A high-bandwidth PLL can quickly lock
onto a reference clock and react to any changes in the clock. It also allows
a wide band of input jitter spectrum to pass to the output. A
low-bandwidth PLL takes longer to lock, but it attenuates all
high-frequency jitter components. The Quartus II software can adjust
PLL characteristics to achieve the desired bandwidth. The programmable
bandwidth is tuned by varying the charge pump current, loop filter
resistor value, high frequency capacitor value, and m counter value. You
can manually adjust these values if desired. Bandwidth is programmable
from 150 kHz to 2 MHz.
PFD
÷m
Charge
Pump
Δt
Loop
Filter
VCO
All Output Counters and
Clock Delay Settings can
be Programmed Dynamically
÷g
÷e
÷l
Altera Corporation
February 2005
Δt
Δt
Δt