EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 86

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

TriMatrix Memory
4–20
Stratix GX Device Handbook, Volume 1
occurs or just read the don’t care bits. Single-port memory supports
non-simultaneous reads and writes, but the q[] port outputs the data
once it has been written to the memory (if the outputs are not registered)
or after the next rising edge of the clock (if the outputs are registered). For
more information, see the TriMatrix Embedded Memory Blocks in
Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook,
Volume 2.
configurations for TriMatrix memory.
Figure 4–12. Simple Dual-Port & Single-Port Memory Configurations
Note to
(1)
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
TriMatrix memory architecture can implement pipelined RAM by
registering both the input and output signals to the RAM block. All
TriMatrix memory block inputs are registered providing synchronous
write cycles. In synchronous operation, the memory block generates its
own self-timed strobe write enable (WREN) signal derived from the global
Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
Figure
Simple Dual-Port Memory
Single-Port Memory (1)
Figure 4–12
4–12:
data[ ]
wraddress[ ]
wren
inclocken
inaclr
data[ ]
address[ ]
wren
inclocken
inaclr
inclock
inclock
shows these different RAM memory port
rdaddress[ ]
outclocken
outclocken
outclock
outclock
outaclr
outaclr
rden
q[ ]
q[ ]
Altera Corporation
February 2005