EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 48

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Other Transceiver Features
2–38
Stratix GX Device Handbook, Volume 1
rxdigitalreset
rxanalogreset
txdigitalreset
pll_areset
pllenable
Table 2–11. Reset Signal Map to Stratix GX Blocks
Reset Signal
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Power-down functions are static, in other words., they are implemented
upon device configuration and programmed, through the Quartus II
software, to static values. Resets can be static as well as dynamic inputs
coming from the logic array or pins.
Voltage Reference Capabilities
Stratix GX transceivers provide voltage reference and bias circuitry. To
set-up internal bias for controlling the transmitter output drivers’ voltage
swing—as well as to provide voltage/current biasing for other analog
circuitry—use the internal bandgap voltage reference at 0.7 V. To provide
bias for internal pull-up PMOS resistors for I/O termination at the serial
interface of receiver and transmitter channels (independent of power
supply drift, process changes, or temperature variation) an external
resistor, which is connected to the external low voltage power supply, is
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Altera Corporation
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June 2006
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