EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 160

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

PLLs & Clock Networks
Figure 4–57. Stratix GX Device Fast PLL
Notes to
(1)
(2)
4–94
Stratix GX Device Handbook, Volume 1
Global or
regional clock (1)
Clock
Input
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Figure
4–57:
Frequency
Detector
Clock Multiplication & Division
The Stratix GX device’s fast PLLs provide clock synthesis for PLL output
ports using m/(post scaler) scaling factors. The input clock is multiplied
by the m feedback factor. Each output port has a unique post scale counter
to divide down the high-frequency VCO. There is one multiply divider,
m, per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed differential interface, you can set the output
counter to 1 to allow the high-speed VCO frequency to drive the SERDES.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or for general-purpose external clocks.
There are no dedicated external clock output pins. Any I/O pin can be
driven by the fast PLL global or regional outputs as an external output
Phase
PFD
Charge
Pump
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
÷ m
VCO
8
Post-Scale
Counters
÷l0
÷l1
÷g0
Altera Corporation
February 2005
diffioclk1 (2)
Global or
regional clock
txload_en
rxload_en
Global or
regional clock
diffioclk2 (2)
Global or
regional clock