EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 168

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

I/O Structure
Figure 4–63. Stratix GX IOE in Bidirectional I/O Configuration
Note to
(1)
4–102
Stratix GX Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
Figure
I/O Interconnect
[15..0]
4–63:
ioe_clk[7..0]
OE
clkout
ce_out
aclr/prn
clkin
ce_in
sclr/preset
The Stratix GX device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Chip-Wide Reset
Register Delay
Logic Array
Enable Clock
Enable Delay
Output Clock
Enable Delay
to Output
Output
Enable Delay
Input Clock
Output Register
Input Register
OE Register
D
ENA
CLRN/PRN
ENA
D
ENA
CLRN/PRN
D
CLRN/PRN
Q
Q
Q
Drive Strength Control
Pin Delay
Output
Note (1)
Open-Drain Output
Input Register Delay
Logic Array Delay
Slew Control
Input Pin to
Input Pin to
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Optional
PCI Clamp
V
Altera Corporation
CCIO
Bus-Hold
February 2005
Circuit
Programmable
Pull-Up
Resistor