EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 238

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Timing Model
6–36
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
t
INSU
INH
OUTCO
Table 6–51. Stratix GX Fast Regional Clock External I/O Timing Parameters
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device
and speed grade and whether it is t
for any pin.
Table
6–51:
Setup time for input or bidirectional pin using column IOE
input register with fast regional clock fed by
Hold time for input or bidirectional pin using column IOE
input register with fast regional clock fed by
Clock-to-output delay output or bidirectional pin using
column IOE output register with fast regional clock fed by
FCLK
pin
Figure 6–6. External Timing in Stratix GX Devices
All external I/O timing parameters shown are for 3.3-V LVTTL or
LVCMOS I/O standards with the maximum current strength. For
external I/O timing using standards other than LVTTL or LVCMOS use
the I/O standard input and output delay adders in
6–76.
Table 6–51
regional clock networks.
Dedicated
Clock
CO
Parameter
or t
shows the external I/O timing parameters when using fast
SU
. You should use the Quartus II software to verify the external timing
FCLK
FCLK
Output Register
Input Register
OE Register
D
D
D
pin
pin
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
C
L O A D
Notes
= 10 pF
Tables 6–72
Conditions
(1),
Altera Corporation
t
t
t
INSU
INH
OUTCO
(2)
Bidirectional
Pin
June 2006
through