EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 172

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

I/O Structure
Figure 4–66. Stratix GX IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
4–106
Stratix GX Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
The tristate is by default active high. It can, however, be designed to be active low.
I/O Interconnect
Figure
[15..0]
IOE_CLK[7..0]
4–66:
clkout
aclr/prn
sclr
Chip-Wide Reset
Register Delay
Register Delay
Logic Array
Enable Delay
Enable Delay
Enable Clock
Output Clock
Logic Array
to Output
to Output
Output
Output Register
Output Register
OE Register
OE Register
ENA
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Notes
Drive Strength Control
Used for
DDR SDRAM
Pin Delay
Output
Open-Drain Output
(1),
Slew Control
(2)
clk
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
V
CCIO
Optional
PCI Clamp
February 2005
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor