EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 33

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Figure 2–19. Before & After the Channel Aligner
Rate Matcher
The rate matcher, which is available only in XAUI and GIGE modes,
consists of a 12-word deep FIFO buffer and a FIFO controller. The rate
matcher is bypassed when the device is not in XAUI or GIGE mode.
In a multi-crystal environment, the rate matcher compensates for up to a
100-ppm difference between the source and receiver clocks.
GIGE Mode
In the GIGE mode, the rate matcher adheres to the specifications in
clause 36 of the IEEE 802.3 documentation, for idle additions or removals.
The rate matcher performs clock compensation only on /I2/ ordered
sets, composing a /K28.5/+ followed by a /D16.2/-. The rate matcher
does not perform a clock compensation on any other ordered set
combinations. An /I2/ is added or deleted automatically based on the
number of words in the FIFO buffer. A 9’h19C is given at the control and
data ports when the FIFO is in an overflow or underflow condition.
Lane 0
Lane 0
Lane 0
Lane 0
Lane 0
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Lane 0
Lane 0
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Stratix GX Device Handbook, Volume 1
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Stratix GX Transceivers
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2–23
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