EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 173

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 4–67. Output Timing Diagram in DDR Mode
Altera Corporation
February 2005
From Internal
Registers
DDR output
f
CLK
A
B
The Stratix GX IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. Stratix GX device I/O pins
transfer data on a DDR bidirectional bus to support DDR SDRAM. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock. This is done to meet DDR SDRAM timing
requirements.
External RAM Interfacing
Stratix GX devices support DDR SDRAM at up to 200 MHz (400-Mbps
data rate) through dedicated phase-shift circuitry, QDR and QDRII
SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200
MHz. Stratix GX devices also provide preliminary support for reduced
latency DRAM II (RLDRAM II) at rates up to 200 MHz through the
dedicated phase-shift circuitry.
1
To find out more about the DDR SDRAM specification, see the JEDEC
web site (www.jedec.org). For information on memory controller
megafunctions for Stratix GX devices, see the Altera web site
(www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix &
Stratix GX Devices for more information on DDR SDRAM interface in
Stratix GX. Also see AN 349: QDR SRAM Controller Reference Design for
Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices.
In addition to the required signals for external memory
interfacing, Stratix GX devices offer the optional clock enable
signal. By default the Quartus II software sets the clock enable
signal high, which tells the output register to update with new
values. The output registers hold their own values if the design
sets the clock enable signal low. See
A1
B1
B1
A2
B2
A1
B2
A3
B3
A2
B3
Stratix GX Device Handbook, Volume 1
A4
B4
A3
Figure
Stratix GX Architecture
4–63.
4–107