EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 65

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
August 2005
To manage the alignment procedure, a state machine should be built in
the FPGA logic array to generate the realignment signal. The following
guidelines outline the requirements for this state machine.
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The design must include an input synchronizing register to ensure
that data is synchronized to the ×W/J clock.
After the state machine, use another synchronizing register to
capture the generated rx_channel_data_align signal and
synchronize it to the ×W/J clock.
Because the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two W/J clock periods.
To guarantee the state machine does not incorrectly generate
multiple rx_channel_data_align pulses to shift a single bit, the
state machine must hold the rx_channel_data_align signal low
for at least three ×1 clock periods between pulses.
Source-Synchronous Signaling With DPA
Stratix GX Device Handbook, Volume 1
3–15