EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 53

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 3–1. Stratix GX High-Speed Interface Deserialized in
Notes to
(1)
(2)
Figure 3–2. Receiver Timing Diagram
Altera Corporation
August 2005
RXCLKIN+
RXCLKIN−
W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA).
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
This figure does not show additional circuitry for clock or data manipulation.
Internal ×10 clock
Internal ×1 clock
RXIN+
RXIN−
Figure
RXLOADEN
data input
Receiver
3–1:
Receiver Circuit
n – 1
PLL (2)
Stratix GX Differential I/O Transmitter Operation
You can configure any of the Stratix GX differential output channels as a
transmitter channel. The differential transmitter serializes outbound
parallel data.
Fast
Serial Shift
Registers
n – 0
RXLOADEN
TXLOADEN
× W
9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
8
Registers
Parallel
7
6
×
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
× W / J (1)
10 Mode
Source-Synchronous Signaling With DPA
5
Stratix GX Device Handbook, Volume 1
Registers
Parallel
4
3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
2
1
Logic Array
Stratix GX
0
3–3