EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 185

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
February 2005
Notes to
(1)
(2)
Differential termination (1),
Table 4–29. Differential Termination Supported by I/O Banks
Differential Termination Support
Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination.
Differential termination is only supported for LVDS because of a 3.3-V V
Table
4–29:
(2)
Figure 4–70. LVDS Input Differential On-Chip Termination
I/O banks on the left and right side of the device support LVDS receiver
(far-end) differential termination.
Table 4–29
Table 4–30
The differential on-chip resistance at the receiver input buffer is
118
Top and bottom I/O banks (3, 4, 7, and 8)
DIFFIO_RX[]
CLK[0,2,9,11],CLK[4-7],CLK[12-15]
CLK[1,3,8,10]
FCLK
FPLL[7..10]CLK
Table 4–30. Differential Termination Support Across Pin Types
Ω ±
20 %.
I/O Standard Support
Transmitting
shows the Stratix GX device differential termination support.
shows the termination support for different pin types.
Device
+
Ð
LVDS
Pin Type
Banks (3, 4, 7 & 8)
Z
Z
Top & Bottom
0
0
Stratix GX Device Handbook, Volume 1
C C I O
.
Differential Termination
Receiving Device with
R
D
Stratix GX Architecture
Left Banks (1 & 2)
+
Ð
v
R
v
v
D
4–119