EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 246

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Timing Model
6–44
Stratix GX Device Handbook, Volume 1
t
t
t
t
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 class I
SSTL-3 class II
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 6–71. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2)
Table 6–72. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
Symbol
I/O Standard
2.000
1.126
0.000
0.500
Min
-5 Speed Grade
External I/O Delay Parameters
External I/O delay timing parameters, both for I/O standard input and
output adders and programmable input and output delays, are specified
by speed grade, independent of device density.
Tables 6–72
and row I/O pins. If an I/O standard is selected other than LVTTL 24 mA
with a fast slew rate, add the selected delay to the external t
parameters.
-5 Speed Grade
Min
5.365
2.304
Max
through
Max
150
210
220
220
120
–30
–30
30
0
0
0
0
0
0
0
2.000
1.186
0.000
0.500
Min
-6 Speed Grade
6–77
-6 Speed Grade
Min
show the adder delays associated with column
5.775
2.427
Max
Max
157
220
231
231
126
–32
–32
31
0
0
0
0
0
0
0
2.000
1.352
0.000
0.500
Min
-7 Speed Grade
-7 Speed Grade
Min
6.621
2.765
Max
Altera Corporation
Max
180
252
265
265
144
–37
–37
CO
35
0
0
0
0
0
0
0
and t
June 2006
Unit
SU
ns
ns
ns
ns
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
I/O