EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 13

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains the following:
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The receiver contains the following:
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You can set all the Stratix GX transceiver functions through the Quartus II
software. You can set programmable pre-emphasis, programmable
equalizer, and programmable V
transceiver channel is also capable of BIST generation and verification in
addition to various loopback modes.
for the Stratix GX transceiver channel.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10-gigabit XAUI and GIGE. The PCS portion of the transceiver consists of
the logic array interface, 8B/10B encoder/decoder, pattern detector, word
aligner, rate matcher, channel aligner, and the BIST and pseudo-random
binary sequence pattern generator/verifier. The PMA portion of the
transceiver consists of the serializer/deserializer, the CRU, and the I/O
buffers.
Transmitter PLL
Transmitter phase compensation FIFO buffer
Byte serializer
8B/10B encoder
Serializer (parallel to serial converter)
Transmitter output buffer
Input buffer
Clock recovery unit (CRU)
Deserializer
Pattern detector and word aligner
Rate matcher and channel aligner
8B/10B decoder
Receiver logic array interface
OD
dynamically as well. Each Stratix GX
Stratix GX Device Handbook, Volume 1
Figure 2–2
shows the block diagram
Stratix GX Transceivers
2–3