EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 239

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
INSU
INH
OUTCO
INSUPLL
Table 6–52. Stratix GX Regional Clock External I/O Timing Parameters
Table 6–53. Stratix GX Global Clock External I/O Timing Parameters (Part 1 of 2)
Symbol
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external
timing for any pin.
Table
6–52:
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by
Clock-to-output delay output or bidirectional pin using
column IOE output register with regional clock fed by
pin
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
Clock-to-output delay output or bidirectional pin using
column IOE output register with regional clock Enhanced
PLL with default phase setting
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by
Clock-to-output delay output or bidirectional pin using
column IOE output register with global clock fed by
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by Enhanced PLL with
default phase setting
Table 6–52
regional clock networks.
Table 6–53
clock networks.
Parameter
Parameter
shows the external I/O timing parameters when using global
shows the external I/O timing parameters when using
CLK
CLK
CLK
CLK
pin
pin
pin
pin
CLK
Stratix GX Device Handbook, Volume 1
CLK
pin
DC & Switching Characteristics
C
C
C
Notes
L O A D
L O A D
L O A D
(1),
= 10 pF
= 10 pF
= 10 pF
Conditions
Conditions
(2)
Notes
(1),
(2)
6–37