EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 85

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
February 2005
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 4–11
Figure 4–11. True Dual-Port Memory Configuration
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
Notes to
(1)
(2)
Configurations
Table 4–2. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
See the DC & Switching Characteristics chapter of the Stratix GX Device Handbook,
Volume 1 for maximum performance information.
The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix GX device must write to the dual-port memory once and then disable the
write-enable ports afterwards.
Table
shows true dual-port memory.
4–2:
data
address
wren
clocken
q
aclr
A
clock
[ ]
512
256
128
64
64
32
32
A
M512 RAM Block
A
A
[ ]
(32 × 18 Bits)
×
×
×
×
A
A
A
×
×
×
[ ]
8
9
16
18
A
1
2
4
Stratix GX Device Handbook, Volume 1
4K
2K
1K
512
512
256
256
128
128
M4K RAM Block
(128 × 36 Bits)
×
×
×
×
×
×
×
×
×
1
2
4
B
address
8
9
16
18
32
36
clocken
clock
data
wren
aclr
q
Stratix GX Architecture
B
B
B
B
[ ]
[ ]
[ ]
B
B
B
64K
64K
32K
32K
16K
16K
8K
8K
4K
4K
(4K × 144 Bits)
M-RAM Block
×
×
×
×
×
×
×
×
×
×
64
72
128
144
8
9
16
18
32
36
4–19