EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 34

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–24
Stratix GX Device Handbook, Volume 1
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
8B/10B Decoder
The 8B/10B decoder converts the 10-bit encoded code group into 8-bit
data and 1 control bit. The 8B/10B decoder can be bypassed. The
following is a diagram of the conversion from a 10-bit encoded code
group into 8-bit data + 1-bit control.
Figure 2–20. 8B/10B Decoder Conversion
There are two optional error status ports available in the 8B/10B decoder,
rx_errdetect and rx_disperr.
ports from a given error. These status signals are aligned with the code
group in which the error occurred.
No errors
Invalid code groups
Disparity errors
Table 2–7. Error Signal Values
Types of Errors
Parallel data
MSB received last
9
j
h
8
H
7
g
7
G
6
rx_errdetect
8b-10b conversion
6
5
F
f
1’b0
1’b1
1’b1
E
4
5
i
Table 2–7
D
3
e
4
2
C
d
3
shows the values of the
1
B
c
2
LSB received first
0
A
b
1
rx_disperr
Altera Corporation
+
1’b0
1’b0
1’b1
a
0
ctrl
June 2006