EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 25

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Figure 2–12. External Termination & Biasing Circuit
Programmable Equalizer
The programmable equalizer module boosts the high frequency
components of the incoming signal to compensate for losses in the
transmission medium. There are five possible equalization settings (0, 1,
2, 3, 4) to compensate for 0”, 10”, 20”, 30”, and 40” of FR4 trace. These
settings should be interpreted loosely. The programmable equalizer can
be set dynamically or statically.
Receiver PLL & CRU
Each transceiver block has four receiver PLLs and CRUs, each of which is
dedicated to a receive channel. If the receive channel associated with a
particular receiver PLL or CRU is not used, then the receiver PLL or CRU
is powered down for the channel.
PLL and CRU circuits.
50/60/75- Ω
Termination
Resistance
Transmission
Line
Receiver External Termination
and Biasing
V
DD
Receiver External Termination
× {R2/(R1 + R 2)} = 1.1 V
R1/R2 = 1K
V
C1
and Biasing
DD
Figure 2–13
Stratix GX Device Handbook, Volume 1
R2
is a diagram of the receiver
R1
Stratix GX Transceivers
Stratix GX Device
RXIN
RXIP
Receiver
2–15