EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 60

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Introduction
Figure 3–8. DPA Receiver Circuit
Note to
(1)
3–10
Stratix GX Device Handbook, Volume 1
dpll_reset
inclk+
inclk -
rxin+
rxin-
These are phase-matched and retimed high-speed clocks and data.
Figure
DPA Receiver Circuit
3–8:
8
Fast PLL
Dynamic
Selector
Phase
×1 Clock
×W Clock (1)
DPA Operation
The DPA receiver circuitry contains the dynamic phase selector, the
deserializer, the synchronizer, and the data realigner (see
This section describes the DPA operation, synchronization and data
realignment. In the SERDES with DPA mode, the source clock is fed to the
fast PLL through the dedicated clock input pins. This clock is multiplied
by the multiplication value W to match the serial data rate.
For information on the deserializer, see
Operation” on page
Serial Data (1)
The dynamic phase selector matches the phase of the high-speed clock
and data before sending them to the deserializer.
The fast PLL supplies eight phases of the same clock (each a separate tap
from a four-stage differential VCO) to all the differential channels
associated with the selected fast PLL. The DPA circuitry inside each
channel locks to a phase closest to the serial data’s phase and sends the
retimed data and the selected clock to the deserializer. The DPA circuitry
automatically performs this operation and is not something you select.
Each channel’s DPA circuit can independently choose a different clock
phase. The data phase detection and the clock phase selection process is
automatic and continuous. The eight phases of the clock give the DPA
circuit a granularity of one eighth of the unit interval (UI) or 125 ps at
1 Gbps.
circuitry and their relationship to a data stream.
Deserializer
Figure 3–9
Parallel
10
Clock
illustrates the clocks generated by the fast PLL
3–1.
Synchronizer
10
“Principles of SERDES
Realigner
Data
Stratix GX Logic Array
RCLK
Altera Corporation
GCLK
Reset
Figure
August 2005
3–8).