EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 162

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

I/O Structure
I/O Structure
4–96
Stratix GX Device Handbook, Volume 1
Phase Shifting
Stratix GX device fast PLLs have advanced clock shift capability that
enables programmable phase shifts. You can enter a phase shift (in
degrees or time units) for each PLL clock output port or for all outputs
together in one shift. You can perform phase shifting in time units with a
resolution range of 150 to 400 ps. This resolution is a function of the VCO
period.
Control Signals
The fast PLL has the same lock output, pllenable input, and areset
input control signals as the enhanced PLL.
For more information on high-speed differential I/O support, see the
High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX
Devices chapter of the Stratix GX Device Handbook, Volume 2.
IOEs provide many features, including:
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The IOE in Stratix GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer.
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Differential on-chip termination for LVDS I/O standard
Programmable pull-up during configuration
Output drive strength control
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double-data rate (DDR) Registers
Figure 4–58
shows the Stratix GX IOE structure. The
Altera Corporation
February 2005