EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 232

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Timing Model
Figure 6–4. Dual-Port RAM Timing Microparameter Waveform
6–30
Stratix GX Device Handbook, Volume 1
unreg_data-out
reg_data-out
wraddress
rdaddress
data-in
rdclock
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
an
din
Figure 6–4
and M-RAM timing parameters shown in
t
t
R X _ F R E Q L O C K
R X _ F R E Q L O C K 2 P H A S E L O C K
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 2 of 2)
t
doutn-1
WEREH
doutn
a0
b0
Symbol
shows the TriMatrix memory waveforms for the M512, M4K,
t
t
DATACO1
WEREH
t
DATACO2
a1
t
RC
doutn
dout0
The time until the clock recovery unit (CRU)
switches to data mode from lock to reference
mode.
The time until CRU phase locks to data after
switching from lock to data mode.
a2
b1
t
t
WADDRSU
a3
WERESU
dout0
Tables 6–39
Parameter
din4
a4
b2
through 6–41.
Altera Corporation
t
WADDRH
din5
a5
June 2006
b3
din6
a6