EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 189

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
February 2005
Note to
(1)
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
SignalTap
instructions
EP1SGX10
EP1SGX25
Table 4–33. Stratix GX JTAG Instructions (Part 2 of 2)
Table 4–35. 32-Bit Stratix GX Device IDCODE (Part 1 of 2)
JTAG Instruction
Device
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(1)
Table
4–33:
Version (4 Bits)
0000
0000
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Stratix GX device through the JTAG port with a MasterBlaster
or ByteBlasterMV
embedded processor.
Emulates pulsing the
pin is unaffected.
Allows the IOE standards to be configured through the JTAG chain. Stops configuration if
executed during configuration. Can be executed before or after configuration.
Monitors internal device operation with the SignalTap embedded logic analyzer.
The Stratix GX device instruction register length is 10 bits, and the
USERCODE register length is 32 bits.
boundary-scan register length and IDCODE information for Stratix GX
devices.
Table 4–34. Stratix GX Boundary-Scan Register Length
0010 0000 0100 0001
0010 0000 0100 0011
Part Number (16 Bits)
TM
download cable, or when using a
nCONFIG
EP1SGX10
EP1SGX25
EP1SGX40
Device
IDCODE (32 Bits)
pin low to trigger reconfiguration even though the physical
Description
Manufacturer Identity
Stratix GX Device Handbook, Volume 1
(1)
000 0110 1110
000 0110 1110
Tables 4–34
Boundary-Scan Register Length
(11 Bits)
.jam
file or
and
Stratix GX Architecture
1,029
1,665
1,941
.jbc
4–35
file with an
LSB (1 Bit)
show the
1
1
4–123
(2)
TM