EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 190

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
4–124
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
EP1SGX40
Table 4–35. 32-Bit Stratix GX Device IDCODE (Part 2 of 2)
Device
The most significant bit (MSB) is at the left end of the string.
The IDCODE’s least significant bit (LSB) is always 1.
Table
4–35:
Version (4 Bits)
0000
Figure 4–72
Figure 4–72. Stratix GX JTAG Waveforms
Table 4–36
devices.
t
t
t
t
Captured
Symbol
J C P
J C H
J C L
J P S U
Table 4–36. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2)
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
0010 0000 0100 0101
Part Number (16 Bits)
TCK
TCK
TCK
JTAG port setup time
shows the JTAG timing parameters and values for Stratix GX
shows the timing requirements for the JTAG signals.
t
clock period
clock high time
clock low time
JCH
t
t
JPZX
JSZX
t
JCP
IDCODE (32 Bits)
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
Manufacturer Identity
(1)
000 0110 1110
t
JPSU
(11 Bits)
t
t
JSXZ
JPH
100
50
50
20
Min (ns) Max (ns)
Altera Corporation
LSB (1 Bit)
t
February 2005
JPXZ
1
(2)