EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 36

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 2–21. Data Path in Serial Loopback Mode
2–26
Stratix GX Device Handbook, Volume 1
Deserializer
Active Path
Non-Active Path
Recovery
Clock
Unit
Serializer
Aligner
Word
Loopback Modes
The Stratix GX transceiver has built-in loopback modes to aid in debug
and testing. The loopback modes are set in the Stratix GX MegaWizard
Plug-In Manager in the Quartus II software. Only one loopback mode can
be set at any single instance of the transceiver block. The loopback mode
applies to all used channels in a transceiver block.
The available loopback modes are:
■
■
■
Serial Loopback
Serial loopback exercises all the transceiver logic except for the output
buffer and input buffer. The loopback function is dynamically switchable
through the rx_slpbk port on a channel by channel basis. The V
output reduced. If you select 400 mV, the output is tri-stated when the
serial loopback option is selected.
serial loopback mode.
Channel
Aligner
BIST PRBS
Verifier
Serial loopback
Parallel loopback
Reverse serial loopback
BIST PRBS
Generator
Encoder
8B/10B
Matcher
Rate
Serializer
Byte
Decoder
8B/10B
Figure 2–21
Compensation
Phase
FIFO
Deserializer
Byte
shows the data path in
Altera Corporation
Incremental
Verifier
Compensation
BIST
Phase
FIFO
June 2006
OD
Generator
BIST
of the